Logic gate having low power consumption

ABSTRACT

A semiconductor logic circuit device uses a plurality of MESFETs and a Schottky barrier diode (11) interconnected in such a way that one MESFET forms a switching input (9), another MESFET may form a load (8), still another MESFET forms a buffer amplifier stage (10), a further MESFET forms a current source, and the Schottky barrier diode operates as a speed-up capacitor for increasing the response characteristic of the buffer stage. Different types of logic circuits may be formed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, specifically toan integrated circuit employing a Schottky gate field effect transistor(metal-semiconductor field effect transistor MESFET). More specifically,it relates to a circuit construction of a logic gate composed of MESFETsusing compound semiconductors.

2. Description of the Prior Art

An integrated circuit employing silicon (Si) as a semiconductor materialis inferior to an integrated circuit employing a compound semiconductorsuch as GaAs as a semiconductor material, with regard to the speed ofoperation the power consumption, etc. A compound semiconductorintegrated circuit formed of GaAs or the like has superiorcharacteristics such as an increased speed of operation a reduced powerconsumption. Therefore, utilization of the integrated circuit employinga compound semiconductor to a digital application field is stronglydesired. A compound semiconductor integrated circuit, such as a GaAsintegrated circuit, is composed of Schottky-gate field-effecttransistors (MESFETs) and hence differs from an Si integrated circuit.

Various circuits employing MESFETs have become known for forming a logicgate which is an extremely important circuit component in digitalintegrated circuits.

FIG. 1 shows a structure of a DCFL (direct-coupled FET logic) circuitwhich is one example of a typical conventional logic gate employingMESFETs.

Referring to FIG. 1, the DCFL circuit comprises a normally-off typeMESFET 1 with its gate receiving an input signal, its source beingconnected to the ground, and its drain providing an output signal. Aload 2 is connected between the drain of the MESFET 1 and a power supplyV_(DD). The load 2 may be a resistor or a MESFET.

The DCFL circuit has a small power consumption and therefore it issuitable for a very large scale integrated circuit (VLSI). However, theDCFL circuit has a disadvantage in that it has a small logical swing.More specifically the logical swing of the DCFL circuit output isusually about 500 mV, since the logical high level thereof is clamped bythe forward threshold voltage of the Schottky gate and the logical lowlevel thereof is at a potential slightly higher than the ground level(normally 0.2 V). Consequently, the noise margin and the margin for anythreshold voltage variation of the MESFET are not large enough in theDCFL circuit.

In addition, the low level output potential needs to be sufficiently lowin the DCFL circuit, so that a resistor having a large resistance valueor a MESFET which passes a sufficiently small current, must be used asthe load 2. If the circuit output is taken off between the load 2 andthe drain of the MESFET 1 as shown in FIG. 1, the current drivability ofthe output is small since the load 2 has an effectively large resistancevalue. Specifically, if the DCFL circuit is used as a current source,the drivability of this current source is extremely small.

As described above, the DCFL circuit is not suitable for a circuitcomprising a long wiring and/or a large number of fan-outs or branches.

FIG. 2 shows a structure of a BFL (Buffered FET Logic) circuit which isanother example of a conventional logic gate employing MESFETs.

Referring to FIG. 2, the BFL circuit comprises a combination of aswitching stage performing a switching operation in response to an inputsignal, and a buffer stage for a current amplification and for a levelshift of the switching stage output (i.e. the drain output of the MESFET4).

The switching stage comprises a normally-on type MESFET 4 with its gatereceiving an input signal, its source connected to ground potential andits drain connected to a power supply V_(DD) through the load 3 and tothe gate of the MESFET 5. The load 3 maybe a resistor or a MESFET.

The buffer stage comprises a normally-on type MESFET 5 having its drainconnected to the power supply V_(DD), its gate is connected to the drainof the MESFET 4, and its source is connected to the anode of a Schottkybarrier diode 6. The Schottky barrier diode 6 shifts the level of anoutput signal and has its anode connected to the source of the MESFET 5,its cathode connected to the drain of the MESFET 7, an output terminaland a normally-on type MESFET 7 having its drain connected to thecathode of the diode 6 and its gate and source both connected to apotential V_(CS).

In the BFL circuit, a MESFET having a threshold voltage of -0.5 V to-2.0 V is commonly used, whereby the logical swing of the output becomesas large as about 1.5 V. Since the BFL circuit has a large logicalswing, it provides enough margin for the variation of the thresholdvoltage. The noise margin thereof is also large.

In addition, in the BFL circuit, the normally-on type MESFET which haslarger current drivability compared with the normally-off type MESFET,is used. Furthermore, the BFL circuit has a buffered amplifying stage.Accordingly, the current drivability of the BFL circuit output is largerthan that of the DCFL circuit. The BFL circuit has superiorcharacteristics in the logical swing in the current drivability, etc.However, the power consumption of the BFL circuit is as large as 1 mW toseveral mW per gate. Therefore, the BFL circuit is not suited as acircuit structure forming a large scale integrated circuit.

Further, power is constantly consumed in the buffered amplificationstage in the BFL circuit. Therefore, it is not an effective circuit interms of the gate power consumption with respect to the currentdrivability at the time of gate switching.

In addition, the BFL circuit comprises at least one diode for a levelshift. Therefore, it is difficult to reduce the logical swing of theoutput to a value smaller than 1.5 V.

Generally, the variation of the threshold voltage in a wafer surface hasbeen a problem in fabricating a MESFET IC on a GaAs substrate. The GaAsICs cannot be fabricated with a high yield unless the threshold voltagesin the wafer surface are uniformly distributed. The conventionalfabrication technique results in MESFETs having a substantial variationof threshold voltages, fabrication technique, so that a difficulttechnical problem arises in the application of the DCFL circuit having asmall logical swing as described with reference to FIG. 1, to the GaAsIC. It appears that the threshold voltage of the DCFL circuit is somehowrelated to dislocations in the wafer or to other crystalline defects.However, a direct relationship has not yet been established. Recently,it has become possible to keep variations of the threshold voltage toless than several 10 mV in an IC comprising MESFETs fabricated on a GaAswafer. The reason for these relatively low variations appears to be thatit has become possible to fabricate GaAs single crystals with with asufficiently high uniformity. If the variations of the threshold voltageare several 10 mV, a logical swing as large as 1.5 V in the BFL circuitmeans that the margin for the threshold voltage is too large. Therefore,a power consumption as small as possible is more desirable than thelarge output logical swing of 1.5 V of the BFL circuit. In other words,the large power consumption of the BFL circuit has become a big problem.

SUMMARY OF THE INVENTION

A principal object of the present invention is to eliminate the abovedescribed defects of the prior logic circuits employing MESFETs. Morespecifically, it is the object of the present invention to provide anovel logic gate circuit employing MESFETs which have a small powerconsumption but enough current drivability at the time of the switchingoperation, and which also provide a sufficient logical swing for forminga large scale integrated circuit.

A semiconductor device according to the present invention comprises aswitching stage including a load having its one terminal connected to afirst supply potential and at least one first MESFET connected betweenthe other terminal of the load and a second supply potential. The on/offoperation of the switching stage is controlled in response to an inputsignal. The device further includes a buffer stage comprising a secondMESFET connected to receive the switching stage output at the gate ofthe buffer stage and having one conduction terminal connected to thefirst supply potential, a third MESFET having one conduction terminalconnected to the other conduction terminal of the second MESFET and theother conduction terminal and its gate connected to a third supplypotential. The device also includes a Schottky barrier diode having itscathode connected to the gate of the second MESFET and the switch stageoutput and its anode connected to a junction of the second and thirdMESFETs.

The level shift amount of the switching stage output, by the bufferedamplification stage is determined by properly setting the respectivethreshold voltages or the values of the gate width of the second andthird MESFETs.

In the above described structure, the Schottky barrier diode functionsas a speed up capacitance which ensures a rapid switching operationwhile the second and third MESFETs amplify and level shift the output ofthe switching stage. Accordingly, a logic gate circuit can beimplemented with a proper output logical swing, a low power consumption,a rapid operation, and a high load drivability.

These objects and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional DCFL circuit which is atypical logic gate circuit employing a MESFET.

FIG. 2 is a schematic diagram of a conventional BFL circuit which isanother typical logic gate circuit employing a MESFET.

FIG. 3 is a schematic diagram of a logic gate circuit according to oneembodiment of the present invention.

FIG. 4 is a schematic diagram similar to that of FIG. 3 with a furtherMESFET as a load and showing experimental parameters for confirming theeffect of the logic gate circuit according to the present invention.

FIG. 5 is a graph showing signal transfer characteristics in the circuitarrangement of FIG. 4.

FIG. 6 is a graph showing propagation delay characteristics in thecircuit arrangement shown in FIG. 4 with a capacitive load connectedthereto.

FIG. 7 is a schematic diagram showing the structure of a NOR circuitaccording to the present invention.

FIG. 8 is a schematic diagram showing the structure of a NAND circuitaccording to the present invention.

DESCRIPTION OF PREFERRED EMBODIMENTS AND OF THE BEST MODE OF THEINVENTION

Referring to FIG. 3, the present logic gate circuit forms an inverter,comprising a switching stage for performing a switching operation inresponse to an input signal and a buffer stage for amplifying and levelshifting the switching stage output.

The switching stage comprises a MESFET 9 receiving an input signal at itgate and having its drain connected to one terminal of a load 8, to agate of a MESFET 10, and to the cathode of a Schottky barrier 11. Thesource of the MESFET 9 is connected to ground potential. The load 8having its one terminal connected to the drain of the MESFET 9, has itsother terminal connected to a first supply potential V_(DD).

A Schottky-gate field effect transistor of the normally-off type, or aSchottky-gate field effect transistor operating in a shallow normally-onregion is used as the input MESFET 9. A resistor or a MESFET which is anactive load, is used as the load 8.

The buffer stage comprises a MESFET 10 receiving the switching stageoutput at its gate and having its drain connected to said first supplypotential V_(DD). The source of the MESFET 10 is connected to the drainof a MESFET 12 and to an anode of the Schottky barrier diode 11. TheMESFET 12 has its drain connected to the source of the MESFET 10 and tothe anode of the Schottky barrier diode 11. The source of the MESFET 12is connected to a second supply potential V_(CS). The Schottky barrierdiode 11 is connected with its cathode to the switching stage output atthe gate of the MESFET 10 and with its anode connected to the nodebetween the MESFETs 10 and 12. The MESFET 12 functions as a currentsource.

The Schottky barrier diode 11 is reversely biased and connected betweenthe gate and source of the MESFET 10. This Schottky barrier diode 11operates as a speed-up capacitor for increasing the responsecharacteristic or speed of the buffer stage. The reverse bias potentialfor the Schottky barrier diode 11 is the difference between the bufferstage output potential and the switching output potential, namely, thelevel shift potential caused by the buffer stage.

The difference of the level shift potential caused by the buffer stagecan be readily provided to the extent of about 0.6 V by making the widthof the gate of the MESFET 12 wider than the gate width of the MESFET 10(provided that the gate lengths are the same) or by setting thethreshold voltage of the MESFET 12 more on the on-side than thethreshold voltage of the MESFET 10 (i.e., increasing the absolute valueof the threshold voltage). Therefore, the value of the output logicalswing surely becomes 0.6 to 1.2 V which is necessary and sufficient forimplementing a large scale integrated circuit.

The threshold voltage of the MESFET 9 can be arbitrarily set in a regionranging from normally-off to a shallow normally-on. This is because thebuffer stage provides an input signal which is properly level shifted.Accordingly, in comparison with a conventional DCFL circuit, asufficient margin for a very wide range of variation of the thresholdvoltage can be provided by the present circuit.

The circuit operation is similar to that of a common inverter circuit,namely, an input signal applied to the gate of the MESFET 9 is invertedat the switching stage and then properly level shifted by the bufferstage before the signal appears at the output.

The above described circuit structure provides the following advantages.

(1) The output logical swing is set in a suitable range of 0.6 to 1.2 V.This value is necessary and sufficient for implementing a large scaleintegrated circuit. In addition, even if there are substantialvariations of the threshold voltages of the MESFETs on a wafer surface,the margin for the threshold voltage variation is sufficient, since thelogical swing is larger than 0.6 V.

(2) The reversely biased Schottky barrier diode functions as a speed-upcapacitor. Accordingly, it is superior to a conventional gate device ofa low power consumption type such as a DCFL circuit in the operationspeed and the current drivability at the time of switching, etc.

(3) Since the buffer stage functions as a level shifter, sufficientoperation margin can be obtained even if the logical low level of theswitching stage is set rather high. Therefore, the resistance value ofthe load resistance 8 can be decreased. If an active in the form of aMESFET is used, the value of the current flowing therethrough can beincreased for enhancing the current drivability of the gate circuit.

(4) A speed-up capacitance is provided by the reversely biased Schottkybarrier diode. Accordingly, a large current can flow transiently at theswitching time.

If the gate circuit drives a capacitance load, the function of thespeed-up capacitor is decreased. However, if the speed-up capacitor hasa capacitance several times larger than the load capacitance,degradation of the switching time of the gate circuit derived from theload capacitance, can be constrained.

For example, in a GaAs IC, a length of wire of about 1 mm is equal tothe load capacitance of about 100 fF. Therefore, in this case, severalhundred fF is enough for the capacitance of the speed-up capacitor. Inthe gate circuit according to the present invention, the reverse biasvoltage of the reversely biased Schottky barrier diode functioning as aspeed-up capacitor is about 0.5 V, so that a small area of severalsquare microns can form a capacitor having a necessary and sufficientcapacitance.

(5) In the circuit structure of FIG. 3, MESFETs 10 and 12 can bedesigned such that sufficient current flows therethrough for generatingthe reverse bias voltage of the Schottky barrier diode 11 and fortransmitting the level shifted DC potential. In this case, transientdrive current necessary for switching is supplied through thecapacitance composed of the Schottky barrier diode. What is necessary inthe normal state of the buffer stage is not a large current but thegeneration of a voltage which maintains the reverse bias condition ofthe Schottky barrier diode. Therefore, the current at the normal stateof the buffer stage can be set to be small thereby decreasing the powerconsumption of the buffer stage. Consequently, a circuit having as smallpower consumption as that of the DCFL circuit can be implemented by thecircuit structure of FIG. 3. With the restriction of small powerconsumption of about the same as the DCFL circuit, it provides a highload drivability due to the Schottky barrier diode.

(6) Either the normally-off type or a shallow normally-on type MESFETsmay be employed. However, the circuit can be structured by employingonly the normally-on type MESFETs having a threshold voltage to theextent of -500 mV. In addition, the circuit may be composed of MESFETshaving one value for the threshold voltages. In this case, since thethreshold voltages are of the same value, the wafer process can besimplified.

(7) Conventionally, in the DCFL circuit and the like, it is difficult tofabricate a NAND circuit and a composite gate since the logical swing issmall. However, according to the present invention, a NAND circuit and acomposite gate can be fabricated since the logical swing can beenlarged.

In FIG. 4 the load 8 of the circuit shown in FIG. 3 has been replaced bya load in the form of a further MESFET M2 for demonstrating the effectof the present invention.

In FIG. 4, the gate width of the MESFET M1 is 10 μm, the gate width ofthe MESFET M2 is 25 μm, the gate width of the MESFET M3 is 2 μm and thegate width of the MESFET M4 is 10 μm. The threshold voltages of theMESFETs M1 to M4 are all -0.4 V while the gate length thereof are all1.2 μm.

The source of the MESFET M1 is connected to the potential of -1.5 Vwhile the gate and source of the MESFET M4 are connected to thepotential of -2.5 V.

The drains of the MESFET M2 and M3 are both connected to the groundpotential. MESFETs M2 and M4 function as current sources.

FIG. 5 is a graph showing the signal transmission characteristics in thecircuit shown in FIG. 4. In FIG. 5, the abscissa denotes the inputsignal potential while the ordinate denotes the output signal potential.

The solid line I represents the transfer characteristics of the circuitshown in FIG. 4 while the solid line II represents a curve symmetricalto the solid line I with respect to a line of 45° inclination.

The dotted line III denotes the transfer characteristics of the DCFLcircuit while the dotted line IV represent a curve symmetrical to thedotted line III with respect to the line of 45° inclination. The regionenclosed by the solid lines I and II and the region enclosed by dottedlines III and IV represent the noise margins in the respective circuits.

As can be seen from the solid line I in FIG. 5, by using two powersupplies of -1.5 V and -2.5 V, an output compatible with an ECL (EmitterCoupled Logic) circuit of about -0.8 V to -1.8 V can be obtained. Thisprovides an extremely high practical value in considering the interfacewith an existing high speed logic circuit formed as an Si IC.

As may be seen from the comparison with the transfer characteristics ofthe DCFL circuit, that the logic gate circuit according to the presentinvention has a noise margin more than twice as large as that of theDCFL circuit. Namely, in the GaAs IC using the logic gate circuitaccording to the present invention, the tolerance of the process isextremely large compared with the DCFL circuit, thereby providing a highmanufacturing yield.

FIG. 6 is a graph showing a relation between the capacitance value ofthe capacitive load and the operation speed (propagation delay time) inthe circuit structure of FIG. 4. Referring to FIG. 6, the abscissadenotes the capacitance value of the capacitive load (wiring; fan-out)while the ordinate denotes the propagation delay time (unit: pico sec.).The solid line shows the characteristics of the logic gate circuitaccording to the present invention and the dotted line shows thecharacteristics of the DCFL circuit. The power consumption of the DCFLcircuit is 0.1 mW per gate while the power consumption of the logic gatecircuit according to the present invention is 0.5 mW per gate.

As may be seen from FIG. 6, although the logic gate circuit according tothe present invention has a low power consumption of 0.5 mW/gate, thepropagation delay time thereof is extremely high, e.g., it is about 250pico sec. in driving the wire having 1 mm wire length. As it may be alsoseen from FIG. 6, an LSI (Large Scale Integrated Circuit) having somethousand gates can be implemented by using the logic gate circuitaccording to the present invention. In addition, it is also seen thatthe logic gate circuit according to the present invention operates about2 times as fast as the DCFL circuit for the wiring or fan-out which is atypical capacitive load in a LSI.

FIG. 7 is a schematic diagram of a logic gate circuit according toanother embodiment of the present invention, wherein the switching stageforms a NOR circuit. Namely, MESFETs 9a to 9n receiving input signals Ato N at respective gates are connected in parallel between the load 8and the ground potential. In this circuit structure, the same effect asthat of the above described embodiment can be obtained since the logicalswing is large.

FIG. 8 is a schematic diagram showing a logic gate circuit according tostill another embodiment of the present invention. In FIG. 8, theswitching stage forms a NAND gate. Namely, MESFETs 9a to 9n receivinginput signals A to N at respective gates are connected in series betweenthe load 8 and the ground potential. The same effect as that of theabove described embodiments can be obtained also in this circuitstructure, since the output logical swing is large.

As described above, according to the present invention, a logic gatecircuit having a necessary and sufficient output logical swing, superiorrapid operation characteristics, high load drivability, and low powerconsumption can be implemented since the switching stage is composed ofa load and at least one first MESFET, and the buffer stage foramplifying and level shifting the switching stage output is composed ofthe series connected second and third MESFETs and a Schottky barrierdiode reversely biased and connected between the gate and source of thesecond MESFET.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

What is claimed is:
 1. A semiconductor device fabricated by using acompound semiconductor, comprising a load having a first load terminalconnected to a first potential, and a second load terminal, a firstSchottky gate field effect transistor connected between said second loadterminal and a second potential, said first Schottky field effecttransistor having a first gate for receiving an input signal appliedexternally to said first gate, a second Schottky gate field effecttransistor having first and second conduction terminals and a secondgate, said first conduction terminal being connected to said firstpotential and said second gate being connected to a node between saidfirst Schottky gate field effect transistor and said load, a thirdSchottky gate field effect transistor having third and fourth conductionterminals and a third gate, said third conduction terminal of said thirdSchottky gate field effect transistor being connected directly to saidsecond conduction terminal of said second Schottky gate field effecttransistor, said third gate and said fourth conduction terminal beingconnected together to a third potential, and a Schottky barrier diodehaving a cathode connected to said second gate of said second Schottkygate field effect transistor and an anode connected to said secondconduction terminal of said second Schottky gate field effect transistorand to said third conduction terminal of said third Schottky gate fieldeffect transistor, and wherein said second gate of said second Schottkygate field effect transistor has a gate width which is smaller than agate width of said third Schottky gate field effect transistor, wherebya potential difference is produced as a small level shift voltagebetween said second gate and said second conduction terminal.
 2. Thesemiconductor device of claim 1, wherein said compound semiconductor isgallium arsenide.
 3. The semiconductor device of claim 1, wherein theabsolute value of the threshold voltage of said second Schottky gatefield effect transistor is smaller than that of the threshold voltage ofsaid third Schottky gate field effect transistor.
 4. The semiconductordevice of claim 1, wherein said first Schottky gate field effecttransistor is a single Schottky gate field effect transistor.
 5. Thesemiconductor device of claim 1, wherein said first Schottky gate fieldeffect transistor comprises a plurality of Schottky gate field effecttransistors connected in parallel with each other between said otherconduction terminal of said load and said second potential for receivinginput signals at respective gates.
 6. The semiconductor device of claim1, wherein said first Schottky gate field effect transistor comprises aplurality of Schottky gate field effect transistors connected in serieswith each other between said other conduction terminal of said load andsaid second potential for receiving input signals at respective gates.7. A semiconductor device fabricated by using a compound semiconductor,comprising a load having a first load terminal connected to a firstpotential, and a second load terminal, a first Schottky gate fieldeffect transistor connected between said second load terminal and asecond potential, said first Schottky field effect transistor having afirst gate for receiving an input signal applied externally to saidfirst gate, a second Schottky gate field effect transistor having firstand second conduction terminals and a second gate, said first conductionterminal being connected to said first potential and said second gatebeing connected to a node between said first Schottky gate field effecttransistor and said load, a third Schottky gate field effect transistorhaving third and fourth conduction terminals and a third gate, saidthird conduction terminal of said third Schottky gate field effecttransistor being connected directly to said second conduction terminalof said second Schottky gate field effect transistor, said third gateand said fourth conduction terminal being connected together to a thirdpotential, and a Schottky barrier diode having a cathode connected tosaid second gate of said second Schottky gate field effect transistorand an anode connected to said second conduction terminal of said secondSchottky gate field effect transistor and to said third conductionterminal of said third Schottky gate field effect transistor, andwherein the absolute value of the threshold voltage of said secondSchottky gate field effect transistor is smaller than that of thethreshold voltage of said third Schottky gate field effect transistor,whereby a potential difference is produced as a small level shiftvoltage between said second gate and said second conduction terminal. 8.A semiconductor device fabricated by using a compound semiconductor,comprising a load having a first load terminal connected to a firstpotential, and a second load terminal, a first Schottky gate fieldeffect transistor connected between said second load terminal and asecond potential, said first Schottky field effect transistor having afirst gate for receiving an input signal applied externally to saidfirst gate, a second Schottky gate field effect transistor having firstand second conduction terminals and a second gate, said first conductionterminal being connected to said first potential and said second gatebeing connected to a node between said first Schottky gate field effecttransistor and said load, a third Schottky gate field effect transistorhaving third and fourth conduction terminals and a third gate, saidthird conduction terminal of said third Schottky gate field effecttransistor being connected directly to said second conduction terminalof said second Schottky gate field effect transistor, said third gateand said fourth conduction terminal being connected together to a thirdpotential, and a Schottky barrier diode having a cathode connected tosaid second gate of said second Schottky gate field effect transistorand an anode connected to said second conduction terminal of said secondSchottky gate field effect transistor and to said third conductionterminal of said third Schottky gate field effect transistor, whereinsaid second gate of said second Schottky gate field effect transistorhas a gate width which is smaller than a gate width of said thirdSchottky gate field effect transistor, wherein said second potential isa negative bias potential for said first Schottky gate field effecttransistor, and wherein said third potential is also a negative biaspotential for said third Schottky gate field effect transistor, wherebya potential difference is produced as a small level shift voltagebetween said second gate and said second conduction terminal.
 9. Thesemiconductor device of claim 8, wherein said second negative biaspotential is -1.5 V, and wherein said third negative bias potential is-2.5 V.